1. Field of the Invention
This invention relates to a network of data stations which may be processors, memories and the like, and more particularly to such a network wherein control of the transmission between the stations is embedded in the network.
2. Description of the Prior Art
Prior art networks usually have been controlled by a master controller or computer which receives transmission requests from the respective terminals and grants access to a transmission channel by the individual station when the channel is available and according to some priority arrangement. Such master computers add to the cost of the network and are not required for those networks where the stations need communicate only between themselves or with a common storage file. Thus, it is desirable to have a data network where the transmission control is embedded in or shared by the stations making up that network.
A particular type of network of the prior art is one having a plurality of devices and a time-shared bus over which the devices send messages, the transfer of which is synchronized by a fixed frequency clock signal which is generated by a controller on the line. The controller also determines the priority by which the devices send messages over the bus. To that end, the controller receives a "request" signal from each device over separate control lines and sends a "request granted" signal back to each device over separate control lines. These control lines are not time-shared by the devices.
Also, the controller monitors all messages on the bus to determine if a parity error occurs. If an error does occur, then the controller sends a signal on another separate control line to the device which received the erroneous message.
An undesirable aspect of this type of network is that if a device receives a message which requires a response message to be sent, that response message cannot be sent immediately. Instead, the receiving device must first obtain access to the bus from the bus controller. Typically, several other devices will transmit messages on the bus before the receiving device is permitted to send its response. Thus, a communication between devices on the bus occurs in a random, illogical order.
Another undesirable aspect of the system is that too many separate control lines are required for the operating bus. This drawback is most severe for large systems, because the number of control lines increases as the number of devices increases.
Furthermore, the system is totally dependent on the bus controller for its operation. That is to say, the system simply cannot function when the controller is not operating. This is true even though the devices may be completely operational.
Another data processing network of the prior art includes a time-shared bus in which all message transfers occur between one of the devices and the bus controller. In operation, the bus controller sends spaced-apart polling pulses down a separate control line. A path for these pulses to pass serially through each device is established by the placement of jumper wires. Any device may transmit a message to the controller only after it receives a polling pulse on the line, blocks that pulse from traveling further down the line, and sends a signal to another control line which tells the controller to stop generating pulses until the message is sent. Each device generates its own asynchronous clocking signals on the respective lines to transfer messages on the bus. A device which has no message to send simply allows the pulses on the line to pass to the next device.
Once a device obtains the use of the bus, messages can be sent from that device to the bus controller and the controller can respond by immediately sending another message back to that same device. But the controller, or channel, cannot respond by sending a message back to a second device. Also, one device cannot send a message directly to another device.
The latter network does not utilize as many control lines as does the former network described above. But even so, the latter network still requires some separate control lines and still depends on a separate bus controller for its operation. Furthermore, the above reduction in control lines is obtained only at the cost of making the priority by which a device may obtain the bus very inflexible. That priority is limited by device positions on the bus.
It is, then, an object of the present invention to provide a network of stations employing a single transmission bus, which network does not require a separate bus controller.
It is another object of the present invention to provide a network of stations employing a single transmission bus wherein the bus assignment control line is a single daisy-chained circuit which nevertheless can be expanded to accommodate additional stations.
It is still another object of the present invention to provide a network of stations having a single daisy-chained bus assignment control line which can detect and bypass non-operating stations in the network.
It is still a further object of the present invention to provide a network employing a single data transmission bus which can accommodate overlapping data transmission and acknowledgment signals in a common mode configuration.